A new countermeasure against side-channel attacks based on hardware-software co-design

This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software co-design. The hardware architecture consists of a microprocessor, which executes the algorithm using a false key, and a coprocessor that performs several operations that are necessary to retrieve the original text that was encrypted with the real key. The coprocessor hardly affects the power consumption of the device, so that any classical attack based on such power consumption would reveal a false key. Additionally, as the operations carried out by the coprocessor are performed in parallel with the microprocessor, the execution time devoted for encrypting a specific text is not affected by the proposed countermeasure. In order to verify the correctness of our proposal, the system was implemented on a Virtex 5 FPGA. Different SCA attacks were performed on several functions of AES algorithm. Experimental results show in all cases that the system is effectively protected by revealing a false encryption key.Peer ReviewedPreprin

Hardware architecture implemented on FPGA for protecting cryptographic keys against side-channel attacks

This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using two statistical methods which are based on correlation, the Welch’s t-test and the difference of means.Peer ReviewedPostprint (author's final draft

Modified Vaccinia Virus Ankara as a Viral Vector for Vaccine Candidates against Chikungunya Virus

There is a need to develop a highly effective vaccine against the emerging chikungunya virus (CHIKV), a mosquito-borne Alphavirus that causes severe disease in humans consisting of acute febrile illness, followed by chronic debilitating polyarthralgia and polyarthritis. In this review, we provide a brief history of the development of the first poxvirus vaccines that led to smallpox eradication and its implications for further vaccine development. As an example, we summarize the development of vaccine candidates based on the modified vaccinia virus Ankara (MVA) vector expressing different CHIKV structural proteins, paying special attention to MVA-CHIKV expressing all of the CHIKV structural proteins: C, E3, E2, 6K and E1. We review the characterization of innate and adaptive immune responses induced in mice and nonhuman primates by the MVA-CHIKV vaccine candidate and examine its efficacy in animal models, with promising preclinical findings needed prior to the approval of human clinical trials.This research was supported by the ICRES (Integrated Chikungunya Research), a collaborative project supported by the European Union under the Health Cooperation Work Program of the 7th Framework Program (grant agreement 261202), a grant from the Spanish Ministerio de Ciencia e Innovación (SAF2008-02036), and a grant from Acción Estratégica en Salud from the ISCIII, grant MPY 388/18.S

The Violence after 'La Violencia' in the Ch'orti' Region of Eastern Guatemala

This is the authors' accepted manuscript. The publisher's official version is available from: http://dx.doi.org/10.1111/j.1935-4940.2010.01061.x

Preliminary study on non-viral transfection of F9 (factor IX) gene by nucleofection in human adipose-derived mesenchymal stem cells

Background. Hemophilia is a rare recessive X-linked disease characterized by a deficiency of coagulation factor VIII or factor IX. Its current treatment is merely palliative. Advanced therapies are likely to become the treatment of choice for the disease as they could provide a curative treatment. Methods. The present study looks into the use of a safe non-viral transfection method based on nucleofection to express and secrete human clotting factor IX (hFIX) where human adipose tissue derived mesenchymal stem cells were used as target cells in vitro studies and NOD. Cg-Prkdcscid Il2rgtm1Wjl/SzJ mice were used to analyze factor IX expression in vivo studies. Previously, acute liver injury was induced by an injected intraperitoneal dose of 500 mg/kg body weight of acetaminophen. Results. Nucleofection showed a percentage of positive cells ranging between 30.7% and 41.9% and a cell viability rate of 29.8%, and cells were shown to secrete amounts of hFIX between 36.8 and 71.9 ng/mL. hFIX levels in the blood of NSG mice injected with ASCs transfected with this vector, were 2.7 ng/mL 48 h after injection. Expression and secretion of hFIX were achieved both in vitro cell culture media and in vivo in the plasma of mice treated with the transfected ASCs. Such cells are capable of eventually migrating to a previously damaged target tissue (the liver) where they secrete hFIX, releasing it to the bloodstream over a period of at least five days from administration. Conclusions. The results obtained in the present study may form a preliminary basis for the establishment of a future ex vivo non-viral gene/cellular safe therapy protocol that may eventually contribute to advancing the treatment of hemophilia

Spatial Interpolation contribution to noise maps uncertainty

Noise maps results are usually presented as contour graphs or isophone curves, which describe the sound levels as functions of spatial location. These maps are added to Geographic Information Systems (GIS), allowing sound level evaluation as a function of the continuous coordinates x and y, for a given height above ground. Although the outcome of the system is a continuous variable, the calculations that allow its evaluation are obtained in discrete points that form a calculation grid, which is created by the application of spatial sampling techniques. Using spatial interpolation tools, values are assigned to the locations in which measures or calculations have not been performed. The application of sampling and interpolation techniques (the type of grid, its density, the interpolation algorithms…) contributes to the uncertainty of the results. This paper describes a calculation method to quantify the uncertainty associated to the spatial sampling and interpolation process. We also propose a revision of the classical meaning of noise mapping uncertainty, taking into account the final application of the results

Acceleration of Complex Algorithms on a Fast Reconfigurable Embedded System on Spartan-3

Complex algorithms usually require several computation stages. Many embedded microprocessors have not enough computational performance to resolve these algorithms in a reasonable time, so dedicated coprocessors accelerate them although the main drawback is the area devoted to them. A reconfigurable coprocessor can drastically reduce the area, since it accommodates a set of coprocessors whose execution is multiplexed on time, although the reconfiguration speed reduces the overall system performance. Although self-reconfigurable systems are possible on Spartan-3 FPGAs, it requires a hard design task due to the lack of software and hardware support available on higher-cost families. This paper describes the architecture of a fast self-reconfigurable embedded system mapped on Spartan-3, used as computation platform to solve a complex algorithm, such as the image-processing carried out in a fingerprint biometric algorithm. In order to reduce the reconfiguration time, the system uses our custom-made memory and reconfiguration controllers. Moreover, the dynamic coprocessor can access directly to external memory through our memory controller to improve processing time.Peer ReviewedPostprint (published version

Hardware-software co-design of an iris recognition algorithm

This paper describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32- bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared to a conventional software-based application. Experimental results show that with a clock speed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480 pixels, which is just 20% of the total time needed by a software solution running on the same microprocessor embedded in the architecture.Peer ReviewedPreprin